The present invention relates to a semiconductor device and its manufacturing method and especially, relates to the semiconductor having a field effect transistor and its manufacturing method.
An integrated-circuit fabrication technology using silicone continues making progress at a tremendous speed. The advancement of a micro-fabrication technology has reduced element sizes and enabled the integration of an additional number of elements onto one chip, resulting in an increase in functionality. At the same time, the advanced element micro-fabrication technology has improved their current driving performance while reducing load capacity, achieving higher processing speeds.
As the element sizes have increasingly became small, the thickness of the gate insulating film has been also made thinner. Although the sizes of entire elements may be further made smaller, the thickness of the insulating film made of silicone dioxide, which is the material used for conventional films, virtually has been reduced to its critical limit. The thickness of the thinnest one of existing silicone-dioxide gate insulating films is about 2 nm and making the silicone-dioxide films further thinner may cause a direct tunnel effect, leading to a large leak current. The presence of a large leak current not only increases power consumption but also decrease the number of charges induced in the reverse layer of a channel, which in turn, deteriorates the element""s current driving performance. Moreover, since such a thin silicone dioxide film has lower competency for a diffusion barrier against impurities, a leak of an impurity may occur out of an electrode. Furthermore, since this type of thin silicone dioxide film is formed by multiple atom layers, precise control is critical to mass-manufacture the films with high homogeneity.
Consequently, to ensure that further thinner elements with higher-speed processing performance are realized, xe2x80x9chigh-K materialxe2x80x9d, which provides the same higher level of field effect performance as that of the silicone dioxide even if the films made of them are thicker than the silicone dioxide film, have been proactively developed. Potential candidates for them include IV-group oxides such as zirconia and hafnia, III-group oxides such as alumina and yttria, and cilicates, which are solid solutions of silicone dioxide and any of these metals. IV-group and III-group oxides were used for gate insulating films of Si semiconductors at the early stage. However, after the fabrication technology for gate insulating films using silicone dioxide was established, because of its excellent properties, the silicone dioxide material has been exclusively used. Recently, the examples of semiconductors made of silicone dioxide have been reported; the field effect transistor, which uses zirconia for the gate insulating film, is described in IEDM""99 Tech. Digest pp.145, IEEE, 1999, the field effect transistor, which uses hafnia for the gate insulating film, is descried in 2000 Symposium on VLSI Technology Digest of Technical Papers, and the field effect transistor, which uses alumina for the gate insulating film, is described in IEDM""00 Tech. Digest pp.223, 2000. The method for fabricating metallosilicate is described in, for example, the Official Gazette of JP-A No. H11-135774.
Among them, the materials other than alumina cannot endure high-temperature heat treatment such as activating heat treatment because problems may occur including deterioration in withstand voltage due to a crystallized insulating film, reaction between the gate insulating film and the gate electrode, and a low-dielectric constant layer created on the interface of a Si substrate gate insulating film. Moreover, for the structure, in which a high-dielectric constant gate insulating film and a metal gate electrode are combined, such a problem occurs that the metal electrode has poor heat resistance. One of methods for solving the problem of deterioration due to high-temperature heat treatment is to use a replacement gate process. The replacement gate process is described in, for example, the U.S. Pat. No. 5,960,270. Especially, after a gate electrode pattern is formed in the same manner as a process for manufacturing an ordinary MOSFET, the gate pattern is used as a mask for self-coherent ion plantation of impurities and activating heat treatment to form a diffusion zone. This gate electrode is referred to as a dummy gate because it is peeled off later. By this method, after an interlayer dielectric is formed around the dummy gate, the dummy gate is peeled off to form a groove, a gate insulating film is deposited on the inner wall of the groove, and a metal material is embedded to form the gate electrode. The use of this method can drop the temperatures in the heat treatment process after gate electrode formation.
In addition, in the Official Gazette of JP-A No. 2001-15746xe2x80x3, the method for fabricating the semiconductor device is described, by which a double sidewall consisting of an oxide film and a nitride film is deposited on the sidewall of the dummy gate, the oxide film and the dummy gate insulting film are peeled off from the sidewall, and then a high-dielectric constant gate insulating film is deposited. Even if this method is used, finally the groove gets thick by the thickness of the oxide film on the sidewall.
As the micro-fabrication technology for transistors has advanced, a junction depth must be reduced to suppress the short channel effect. For example, when a gate length reaches 100xe2x88x9250 nm, the junction depth should be reduced to about 30 nm. Since the horizontal enlarged area of an extension is as large as 0.6-0.7 times the junction depth, the overlap between the gate electrode and a source drain is made small accordingly. However, as shown in FIG. 23, a problem may occur that an ON-state drain electric current (ON-current) suddenly decreases when the overlap is reduced to 20 nm or smaller. On the other hand, a too large overlap may cause such problems that since the area, to which a large electric field is applied, is enlarged in OFF state, an OFF current becomes large and the short channel effect is made more severe. To solve the problems, it is required that the junction depth and the overlap length be precisely controlled for micro transistors.
Besides, when the gate insulating film is deposited using the replacement gate process, the insulating film is deposited not only at the bottom but also on the sidewall of the groove. Accordingly, as shown in FIG. 24, the source/drain extension has an offset distance from the gate electrode equal to the thickness of the gate insulating film. If any high-k material is used for the gate insulating film, the ON-current is made small due to a decrease in overlap length because the thickness of the film is about 3-10 nm.
The conventional art described in the above-mentioned Official Gazette of JP-A No. 2001-15746 is intended to protect the sidewall covered with the cap nitride film when the sidewall oxide film and the cap nitride film are peeled off, and not to control the overlap between the source/drain extension and the gate electrode. This means that the conventional art has no technological concept, on which the overlap between the source/drain extension and the gate electrode is controlled. Therefore, in the conventional art, there is no technological concept cannot be found that the thickness of the sidewall oxide film and the thickness of the high-dielectric constant gate insulating film are made almost equal.
An object of the present invention is to provide a semiconductor device, which is a MISFET with a replacement gate electrode, ensuring a large ON-current.
Another objective of the present invention is to provide a method for manufacturing the semiconductor, which can regulate the overlap length of the ISFET with a replacement gate electrode to control a decrease in ON-current.
In order to achieve the above-mentioned objectives, the semiconductor of the present invention is so structured that it has a replacement-gate type of field effect transistor and the length of the overlap between the gate electrode of the field effect transistor and the source/drain diffusion zone is 20 nm or more and 5 nm or more shorter than one half of a channel length.
Further, in order to achieve the above-mentioned objectives, the semiconductor of the present invention is so structured that it has the field effect transistor comprising the gate insulating film deposited on the semiconductor substrate and the gate electrode disposed at the gate insulating film, the insulating film deposited on the side wall of the gate electrode is connected to the gate insulating film to be made from the same material, and the length of the overlap between the gate electrode and the source/drain diffusion zone is 20 nm or more and 5 nm or more shorter than one half of the channel length.
For these semiconductors, high-dielectric constant gate insulating film is preferably used to the gate insulating film.
Further, in order to achieve the above-mentioned objectives, the semiconductor of the present invention is so structured that it has a first field effect transistor and a second field effect transistor disposed on the semiconductor substrate, on the sidewall of the gate electrode of the first field transistor, a first insulating film connecting to the gate insulating film and made of the same material as that for the gate insulating film is deposited, on the sidewall of the gate electrode of the second field effect transistor, the second insulating film is disposed to make the thickness of the first insulating film and the thickness of the second insulating film substantially identical.
In this case, the sentence xe2x80x9cxe2x80x9cwith substantially the same thickness asxe2x80x9d means that they are identical within a tolerance of xc2x15%. Note that it is further preferable that they match within a tolerance of xc2x13%. It is further preferable that the high-dielectric constant gate insulating film is used for the insulating film of the first field effect transistor. It is preferable that the lengths of the overlaps between the gate electrodes of said first and second field effect transistors and the source/drain diffusion zone are 20 nm or more and 5 nm or more shorter than one half of the channel length, respectively. Furthermore, it is preferable that the length of the overlap between the gate electrode of the first field effect transistor and the source/drain diffusion zone is identical to that between the gate electrode of the second field effect transistor and the source/drain diffusion zone.
Further, in order to achieve the above-mentioned objectives, the semiconductor of the present invention is so structured that the first and second field effect transistors are disposed on the substrate, wherein the first field effect transistor is a replacement gate type of field effect transistor and the length of the overlap between the gate electrode of the first field effect transistor and the source/drain diffusion zone is identical to that between the gate electrode of the second field effect transistor and the source/drain diffusion zone.
Further, in order to achieve the above-mentioned objectives, the semiconductor of the present invention is so structured that the first and second field effect transistors are disposed on the substrate, wherein the first insulating film is deposited on the sidewall of the gate electrode of the first field effect transistor and is connected to the gate insulating film, and made of the same material as that for the gate insulating film, and the length of the overlap between the gate electrode of the first field effect transistor and the source/drain diffusion zone is identical to that between the gate electrode of the second field effect transistor and the source/drain diffusion zone.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area on the substrate, where the gate electrode is formed,
a step, in which a source and a drain are formed using the dummy gate electrode as a mask,
a step, in which a first sidewall spacer is formed on the sidewall of the dummy gate electrode and a second sidewall spacer is formed on the sidewall of the first sidewall spacer,
a step, in which an interlayer dielectric covering the dummy gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy electrode and the first sidewall spacer are removed to form a groove having a sidewall of the second sidewall spacer and a bottom of the semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the first sidewall spacer is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate, and
a step, in which the gate electrode is embedded in the groove.
It is preferable that the material for the dummy gate electrode is identical to that for the first sidewall spacer.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area on the substrate, where the gate electrode is formed,
a step, in which the first sidewall spacer is formed on the sidewall of the dummy gate electrode,
a step, in which a source and a drain are formed using the dummy gate electrode and the first sidewall electrode as masks,
a step, in which the second sidewall spacer is formed on the first sidewall spacer and a third sidewall spacer is formed on the second sidewall pacer,
a step, in which the interlayer dielectric covering the dummy gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy electrode and the first and second sidewall spacers are removed to form a groove having a sidewall of the second sidewall spacer,
a step, in which a fourth sidewall spacer is formed on the sidewall of the third sidewall spacer,
a step, in which a portion of the semiconductor between the fourth sidewall spacer and its adjacent sidewall spacers is exposed,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the second sidewall spacer is deposited inside the groove having a bottom of the semiconductor substrate, so as to cover the bottom and sidewall of the groove on the semiconductor substrate, and
a step, in which the gate electrode is embedded in the groove.
It is preferable that the thickness of the first sidewall spacer film is substantially identical to that of the fourth sidewall spacer. Further, it is preferable that the material for the dummy gate electrode is the same as those for the first and second sidewall spacers.
Further, in order to achieve the above-mentioned other objectives, the method of the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area on the substrate, where the gate electrode is formed,
a step, in which a source and a drain are formed using the dummy gate electrode as a mask,
a step, in which a sidewall spacer is formed on the sidewall of the dummy gate electrode,
a step, in which an interlayer dielectric covering the dummy gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy electrode is removed.
a step, in which a portion of the sidewall of the sidewall spacer is scraped off,
a step, in which a portion of the semiconductor substrate between the sidewall spacers is exposed to form the groove having a side wall of a sidewall spacer and a bottom of said semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the sidewall spacer, of which the portion was scraped off in said step for scraping off the portion of the sidewall of said sidewall spacer, is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate, and
a step, in which the gate electrode is embedded in the groove.
Further, in order to achieve the above-mentioned other objectives, the method of the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area on the substrate, where the gate electrode is formed,
a step, in which a source and a drain are formed using the dummy gate electrode as a mask,
a step, in which a first sidewall spacer is formed on the sidewall of the dummy gate electrode,
a step, in which an interlayer dielectric covering the dummy gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed, the top surface of the dummy gate electrode is exposed, and then upper portions of the first and second sidewall spacers are scraped off,
a step, in which the dummy gate electrode and the first sidewall spacer are removed to form a groove having a sidewall of the second sidewall spacer and bottom of the semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the first sidewall spacer is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate, and
a step, in which the gate electrode is embedded in the groove.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area on the substrate, where the gate electrode is formed,
a step, in which a source and a drain are formed by performing ion implantation at an angle using the dummy gate electrode as a mask,
a step, in which the first sidewall spacer is formed on the sidewall of the dummy gate electrode,
a step, in which the interlayer dielectric covering the dummy gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy electrode is removed to form the groove having a sidewall of the first sidewall spacer and a bottom of the semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the first sidewall spacer is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate, and
a step, in which the gate electrode is embedded in the groove.
It is preferable that said ion plantation is performed at any angle ranging from the normal line to the semiconductor substrate to 10-20 degrees.
In said method for manufacturing the semiconductor, the sentence xe2x80x9cwith substantially the same thickness asxe2x80x9d always means that they are identical within a tolerance of xc2x15%. Note that it is further preferable that they match within a tolerance of xc2x13%. It is preferable that the length of the overlap between the gate electrode embedded and the source/drain diffusion zone is 20 nm or more and 5 nm or more shorter than one half of the channel length.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area of a first conductive region on the substrate, where the first gate electrode is formed, and the second gate electrode is formed in the first conductive region,
a step, in which a source and a drain are formed using the dummy gate electrode and the second gate electrode as masks,
a step, in which the first sidewall spacers are formed on the sidewalls of the dummy gate electrode and the second gate electrode and the second sidewall spacer is formed on the sidewall of the first sidewall spacer,
a step, in which the interlayer dielectric covering the dummy gate electrode and the second gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy gate electrode and said first sidewall spacer on the sidewall of the dummy gate electrode are removed to form the groove having a sidewall of the second sidewall spacer and a bottom of the semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the first sidewall spacer is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate, and
a step, in which the first gate electrode is embedded in the groove.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area of a first conductive region on the substrate, where the first gate electrode is formed, and the second gate electrode is formed in the first conductive region,
a step, in which the first sidewall spacers are formed on the sidewalls of the dummy gate electrode and the second gate electrode,
a step, in which a source and a drain are formed using the dummy gate electrode, the first sidewall spacer on the sidewall of the dummy gate electrode, the second dummy electrode, and the first sidewall spacer on the sidewall of the second gate electrode as masks,
a step, in which the second sidewall spacers are formed on the sidewalls of the first sidewall spacer of the dummy gate electrode and of the first sidewall spacer of the second gate electrode are formed, respectively, and then the third sidewall spacers are formed on the sidewalls of the second sidewall spacers,
a step, in which the interlayer dielectric covering the dummy gate electrode and the second gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy electrode and the first and second sidewall spacers on the sidewall of the dummy electrode are removed,
a step, in which the fourth sidewall spacer is formed on the sidewall of the third sidewall spacer on the sidewall of the dummy gate electrode,
a step, in which a portion of the semiconductor substrate between the fourth sidewall spacers are exposed,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the second sidewall spacer is deposited inside the groove having a sidewall of the fourth sidewall spacer and a bottom of semiconductor substrate, so as to cover the bottom and sidewall of the groove, and
a step, in which the first gate electrode is embedded in the groove.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area of a first conductive region on the substrate, where the first gate electrode is formed, and the second gate electrode is formed in the first conductive region,
a step, in which a source and a drain are formed using the dummy gate electrode and the second gate electrode as masks,
a step, in which the sidewall spacers are formed on the sidewalls of the dummy gate electrode and the second gate electrode, respectively,
a step, in which the interlayer dielectric covering the dummy gate electrode and the second gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy gate electrode is removed,
a step, in which a portion of the sidewall of the sidewall spacer of the dummy gate electrode is scraped off,
a step, in which the portion on the semiconductor substrate between the sidewall spacers of the dummy gate electrode is exposed to form the groove having a sidewall of the sidewall spacer and a bottom of said semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the sidewall spacer, of which the portion was scrapes off in the step for scraping off the portion of sidewall spacer, is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate,
a step, in which the first gate electrode is embedded in the groove.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area of a first conductive region on the substrate, where the first gate electrode is formed, and the second gate electrode is formed in the first conductive region,
a step, in which a source and a drain are formed using the dummy gate electrode and the second gate electrode as masks,
a step, in which the first sidewall spacers are formed on the sidewalls of the dummy gate electrode and the second gate electrode, respectively and the second sidewall spacer is formed on the sidewall of the first sidewall spacer,
a step, in which the interlayer dielectric covering the dummy gate electrode and the second gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed and the top surface of the dummy gate electrode is exposed, and the upper portions of the first and second sidewall spacers are scraped off,
a step, in which the dummy gate electrode and the first sidewall spacer are removed to form the groove having a sidewall of the second sidewall spacer and a bottom of the semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the first sidewall spacer is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate,
a step, in which the gate electrode is embedded in the groove.
Further, in order to achieve the above-mentioned other objectives, the method for manufacturing the semiconductor of the present invention comprises;
a step, in which a dummy gate electrode is formed in the area of a first conductive region on the substrate, where the first gate electrode is formed, and the second gate electrode is formed in the first conductive region,
a step, in which a source and a drain are formed by performing ion implantation at an angle using the dummy gate electrode and the second gate electrode as masks, respectively,
a step, in which the first sidewall spacers are formed on the sidewalls of the dummy gate electrode and the second gate electrode, respectively,
a step, in which the interlayer dielectric covering the dummy gate electrode and the second gate electrode is deposited on the semiconductor substrate,
a step, in which the top surface of the interlayer dielectric is smoothed,
a step, in which the top surface of the dummy gate electrode is exposed,
a step, in which the dummy gate electrode is removed to form the groove having a sidewall of the first sidewall spacer on the sidewall of the dummy gate electrode and a bottom of the semiconductor substrate,
a step, in which a high-dielectric constant gate insulating film with substantially the same thickness as that of the first sidewall spacer is deposited, so as to cover the bottom and sidewall of the groove on the semiconductor substrate,
a step, in which the first gate electrode is embedded in the groove.
In the method for manufacturing these semiconductors, the first conductive area is may be N-type region or P-type region. The sentence xe2x80x9cwith substantially the same thickness asxe2x80x9d means that they are identical within a tolerance of xc2x15%. Note that it is further preferable that they match within a tolerance of xc2x13%. In addition, it is preferable that the lengths of the overlaps between the first gate electrode and the source/drain diffusion zone and between the second gate electrodes and the source/drain diffusion zone is 20 nm or more and 5 nm or more shorter than the length of the channel. Moreover, it is preferable that the length of the overlap between the first gate electrode and the source/drain diffusion zone is the same as that between the second gate electrode and the source/drain diffusion zone.